Designed a 16-bit array multiplier using carry save adders and drawing layout in Cadence. Improved performance of multiplier by pipelining multiplier using flip flops and latches.
MS in Electrical & Computer Engg. Seeking entry level positions in the digital hardware sector, i.e. FPGA emulation, VLSI/ASIC Design, Logic Design, Digital Systems & Embedded Systems.
Imagine a world where the chips powering your smartphones, computers, and even cars are designed and tested with unparalleled precision and speed. Welcome to the realm of Very Large Scale Integration ...
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