EDN

Optimizing compression in scan-based ATPG DFT implementations

In the 1990s, Carnegie Mellon researchers created a comprehensive scan-test cost model that demonstrated how design for test (DFT) contributes to profitability (Ref. 1). With scan compression in wide ...
Electronic Design

Scan ATPG and compression are beating Moore’s law

Moore’s law has been the standard reference for semiconductor scaling. It roughly says that semiconductor design sizes, fueled by technology improvements, double every two years. Consequentially, the ...
EDN

The history and future of scan design

For more than four decades, scan technology has somehow eluded the radar screen of the IC test industry. As test continues to evolve and make significant newsworthy changes, scan has maintained a ...
Electronic Design

The Benefits—And Hazards—Of Scan Compression

IC designers now have a powerful weapon in the struggle against rising test costs: commercially available EDA solutions that provide fast and effective means to implement scan compression on-chip. By ...
Design-Reuse

Cost Reduction and Improved TTR with Shared Scan-in DFT CODEC

With advanced technology nodes, the SoCs are growing in density and gate count. This creates challenges regarding the testability, and more importantly, the test cost. The design complexity and size ...
Design-Reuse

Next Gen Scan Compression Technique to overcome Test challenges at Lower Technology Nodes (Part - I)

We live in an era where the demand for portable and wearable devices have been increasing multifold. Products based on applications like IoT (Internet of Things), Artificial Intelligence, Virtual ...