Design-Reuse

SpringSoft Simplifies Verification of Low-power Chips with Advanced Power-aware Debug Solution

New Verdi Power-aware Debug Module enables visualization of power intent with RTL and UPF/CPF for automated debug and analysis HSINCHU, Taiwan, February 8, 2010 - SpringSoft, Inc. (TAIEX: 2473), a ...
EDN

Verdi power-aware debug module enables visualization of power intent

PARIS — SpringSoft introduced a new power-aware debug module for its Verdi automated debug system, accelerating the comprehension of power intent and automating the process of visualizing, tracing and ...
Electronic Design

Solving Six Low-Power Debug Pitfalls

Simulation-based debug challenges arise when verifying the behavior of a power-managed SoC from the front-end design phase through the back-end implementation phase. We'd also like to recognize the ...
Semiconductor Engineering

Efficient Low Power Verification & Debug Methodology Using Power-Aware Simulation

Isolation, retention, and power switches are some of the important functionalities of power-aware designs that use some of the common low power techniques (e.g.) power shutoff, multi-voltage and ...
EDN

Digital Power Debug

Debugging a large system with many power rails can be challenging. However, don’t panic, a PMBus design combined with good software tools can make the job much easier. In this post we will look at a ...