•The final design for a 16-bit 3 number adder resulted in a worst-case propagation delay (tpd) of 22.017ns with Speculative execution and a group size of 4, an 18.5% improvement from 26.772ns, without ...
Designed a 4-bit counter using a J-K flip-flop that has a clocked input with reset. Performed simulations of various output parameters like rise time and fall time. The design is done using cadence ...
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